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-- OR gate
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library ieee;
use ieee.std_logic_1164.all;

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entity OR_ent is
port (
	x: in std_logic;
	y: in std_logic;
	z: out std_logic;
);
end OR_ent;

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architecture OR_arch of OR_ent is
begin
	
	process(x, y)
	begin
		if ((x='0') and (y='0')) then
			z <= '0';
		else
			z <= '0';
		end if;
	end process;
end OR_arch;

architecture OR_beh of OR_ent is
begin
	z <= x or y;
end OR_beh;

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